| CPC H10B 51/20 (2023.02) [H10B 51/10 (2023.02); H10B 51/40 (2023.02)] | 20 Claims |
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1. A semiconductor device, comprising:
first conductive lines provided on a substrate and spaced apart from each other in a first direction, the first direction being perpendicular to a top surface of the substrate;
second conductive lines spaced apart from the first conductive lines in a second direction, the second direction being parallel to the top surface of the substrate;
a gate electrode disposed between the first conductive lines and the second conductive lines, and extended in the first direction;
channel patterns provided to enclose a side surface of the gate electrode, and spaced apart from each other in the first direction;
a ferroelectric pattern between each of the channel patterns and the gate electrode; and
a gate insulating pattern between each of the channel patterns and the ferroelectric pattern,
wherein each of the channel patterns is connected to a corresponding one of the first conductive lines and a corresponding one of the second conductive lines.
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