| CPC H10B 43/40 (2023.02) [G11C 16/24 (2013.01); H10B 41/27 (2023.02); H10B 41/41 (2023.02); H10B 43/27 (2023.02)] | 20 Claims |
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1. A semiconductor device, comprising:
a cell region including
gate electrode layers stacked on a substrate,
channel structures extending in a first direction, the first direction extending perpendicular to an upper surface of the substrate, the channel structures extending through the gate electrode layers, the channel structures connected to the substrate, and
bit lines extending in a second direction, the second direction extending parallel to the upper surface of the substrate, the bit lines connected to the channel structures, the bit lines above the gate electrode layers; and
a peripheral circuit region including page buffers that are connected to the bit lines,
wherein
each of the page buffers includes a first element and a second element, the first element and the second element adjacent to each other in the second direction,
the first element and the second element share a common active region that is located between a first gate structure of the first element and a second gate structure of the second element in the second direction,
the common active region includes boundaries that include an oblique boundary extending in an oblique direction forming an angle that is greater than 0 degrees and less than about 90 degrees with the second direction,
the first gate structure is located between the common active region and a first active region in the second direction, and the second gate structure is located between the common active region and a second active region in the second direction, and
opposite ends of the first active region in a third direction are offset from opposite ends of the second active region in the third direction, the third direction extending perpendicular to the second direction and parallel to the upper surface of the substrate.
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