| CPC H10B 43/27 (2023.02) [H01L 21/02164 (2013.01); H01L 21/0217 (2013.01); H01L 21/31111 (2013.01); H01L 21/31116 (2013.01); H01L 29/66833 (2013.01); H01L 29/7926 (2013.01); H10B 43/10 (2023.02); H01L 21/31144 (2013.01)] | 18 Claims |

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1. A method for manufacturing a semiconductor memory device, comprising:
forming, in a stacked body including a plurality of first layers stacked in a first direction and spaced apart from each other, holes through the stacked body in the first direction, the holes including a first hole, a second hole adjacent to the first hole in a second direction orthogonal to the first direction, and a third hole adjacent to the first hole in a third direction orthogonal to the first direction and oblique to the second direction;
after forming holes, etching at least a first inter-position of the stacked body between the first hole and the second hole, a second inter-position of the stacked body between the first hole and the third hole, and a third inter-position of the stacked body between the second hole and the third hole; and
forming a separation portion separating the stacked body in a fourth direction orthogonal to the first direction and the second direction, the separation portion occupying at least positions of the first to third holes and the first to third inter-positions,
wherein
the holes formed in the stacked body include a first row of the holes and a second row of the holes, the first row and the second row being arranged in the fourth direction and the holes of each row being arranged in the second direction,
the separation portion occupies a position of the first row of the holes and a position of the second row of the holes,
the holes formed in the stacked body further include a third row of the holes, the second row and the third row being arranged in the fourth direction, and
the separation portion further occupies a position of the third row of the holes.
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