| CPC H10B 43/27 (2023.02) [H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 43/10 (2023.02)] | 19 Claims |

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1. A three-dimensional (3D) memory device, comprising:
a memory stack comprising interleaved conductive layers and dielectric layers and comprising a staircase region in a plan view;
a semiconductor layer in contact with the memory stack;
a supporting structure overlapping and arranged within the staircase region of the memory stack to be aligned with the memory stack in a vertical direction of the plan view; and
a source contact structure at a side of the semiconductor layer opposite to the memory stack and in contact with the semiconductor layer,
wherein:
the supporting structure comprises a material other than a material of the semiconductor layer;
a spacer structure is arranged outside the memory stack;
in a lateral direction perpendicular to the vertical direction, the supporting structure is sandwiched within the semiconductor layer without extending to a core array region adjacent to the staircase region;
a contact structure extending vertically and surrounded by the spacer structure;
a stop layer extends, at the side of the semiconductor layer opposite to the memory stack, in the lateral direction, and the supporting structure and the spacer structure terminate on the stop layer; and
the source contact structure penetrates the stop layer to electrically couple with a channel structure through the semiconductor layer.
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