| CPC H10B 41/42 (2023.02) [G06N 3/08 (2013.01); G11C 16/0425 (2013.01); H01L 29/7883 (2013.01)] | 18 Claims |
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1. A system comprising:
an array comprising selected memory cells;
an input block configured to apply, to each selected memory cell, a series of input signals to a terminal of the selected memory cell in response to a series of input bits; and
an output block for generating an output of the selected memory cells, the output block comprising an analog-to-digital converter to convert current from the selected memory cells into a digital value, a shifter, an adder, and a register;
wherein the shifter, adder, and register are configured to receive a series of digital values in response to the series of input bits, shift each digital value in the series of digital values based on a bit location of an input bit within the series of input bits, and add results of the shift to generate an output indicating values stored in the selected memory cells.
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9. A system, comprising:
an array comprising selected memory cells;
an input block configured to apply, for each selected memory cell, a series of input signals to a terminal of the selected memory cells in response to a series of input bits; and
an output block for generating an output of the selected memory cells, the output block comprising an adder for adding output received from the array in response to the series of input bits.
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