US 12,279,427 B2
Semiconductor device and method of fabricating the same
Na-Young Kim, Seoul (KR); Seongho Kim, Seoul (KR); and Hoonmin Kim, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on May 23, 2022, as Appl. No. 17/750,586.
Claims priority of application No. 10-2021-0123994 (KR), filed on Sep. 16, 2021.
Prior Publication US 2023/0084281 A1, Mar. 16, 2023
Int. Cl. H10B 41/42 (2023.01); H10B 41/41 (2023.01)
CPC H10B 41/42 (2023.02) [H10B 41/41 (2023.02)] 10 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a substrate including a cell region and a peripheral region;
landing pads disposed on the cell region and spaced apart from each other in first and second directions that are parallel to a top surface of the substrate and are non-parallel to each other;
contact plugs disposed on the peripheral region and spaced apart from each other in the first and second directions;
a first filler pattern arranged to fill regions between the landing pads and between the contact plugs;
outer voids disposed in the first filler pattern, the outer voids comprising a first outer void on the cell region and a second outer void on the peripheral region;
a second filler pattern arranged to cover the first filler pattern and the contact plugs and to fill at least a portion of the second outer void; and
an inner void positioned in the second outer void and enclosed by the second filler pattern,
wherein the first filler pattern comprises a same material as the second filler pattern,
at least a portion of the second filler pattern on the cell region is located at a level lower than top surfaces of the landing pads, and
a portion of a bottom surface of the second filler pattern on the cell region is exposed by the first outer void.