| CPC H10B 41/35 (2023.02) [G11C 5/06 (2013.01); H01L 29/0649 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/40 (2023.02)] | 20 Claims |
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1. A semiconductor device comprising:
a first active region and a second active region arranged along a first direction in a substrate;
an element isolation layer disposed in the substrate, the element isolation layer extending in a second direction crossing the first direction to isolate the first active region and the second active region;
a first gate electrode extending in the first direction on the first active region;
a second gate electrode extending in the first direction on the second active region; and
an isolation impurity region containing impurities of a first conductivity type in the substrate and disposed below the element isolation layer,
wherein the isolation impurity region includes a first isolation region and a second isolation region spaced apart from each other in the second direction,
at least a part of the substrate interposed between the first gate electrode and the second gate electrode is interposed between the first isolation region and the second isolation region, and is surrounded by the first gate electrode, the first isolation region, the second gate electrode, and the second isolation region from four sides in a plan view, and
the isolation impurity region which overlaps the element isolation layer in a vertical direction surrounds only a part of the first active region in the plan view.
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