US 12,279,424 B2
Semiconductor device and manufacturing method of semiconductor device
Yu Nakane, Kawasaki Kanagawa (JP); Nobuyuki Toda, Kawasaki Kanagawa (JP); Hiroyoshi Kitahara, Yokohama Kanagawa (JP); Takeshi Yamamoto, Kawasaki Kanagawa (JP); and Naozumi Terada, Kawasaki Kanagawa (JP)
Assigned to Kabushiki Kaisha Toshiba, Tokyo (JP); and Toshiba Electronic Devices & Storage Corporation, Tokyo (JP)
Filed by KABUSHIKI KAISHA TOSHIBA, Tokyo (JP); and TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION, Tokyo (JP)
Filed on Feb. 14, 2022, as Appl. No. 17/670,999.
Claims priority of application No. 2021-152203 (JP), filed on Sep. 17, 2021; and application No. 2021-200121 (JP), filed on Dec. 9, 2021.
Prior Publication US 2023/0090702 A1, Mar. 23, 2023
Int. Cl. H01L 27/11521 (2017.01); H01L 27/11568 (2017.01); H01L 29/66 (2006.01); H01L 29/788 (2006.01); H01L 29/792 (2006.01); H10B 41/30 (2023.01); H10B 43/30 (2023.01)
CPC H10B 41/30 (2023.02) [H01L 29/66825 (2013.01); H01L 29/66833 (2013.01); H01L 29/788 (2013.01); H01L 29/792 (2013.01); H10B 43/30 (2023.02)] 7 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a semiconductor substrate;
a charge trap memory transistor comprising at least a first silicon dioxide film, a first silicon nitride film, a second silicon dioxide film, and a first gate electrode positioned on the semiconductor substrate in order, and a third silicon dioxide film formed around side surfaces of the second silicon dioxide film and side surfaces of the first gate electrode; and
a MOS transistor comprising a fourth silicon dioxide film and a second gate electrode positioned on the semiconductor substrate in order, wherein
a thickness of the third silicon dioxide film is 1 to 0.778 (˜35/45) times a thickness of the fourth silicon dioxide film, and any bird's beak is not generated in at least either the first silicon dioxide film or the first gate electrode of the charge trap memory transistor.