| CPC H10B 41/30 (2023.02) [H10B 41/10 (2023.02)] | 20 Claims |
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1. A method of manufacturing a non-volatile memory device, comprising:
providing a substrate;
forming at least one stacked structure on the substrate, wherein the at least one stacked structure comprises a gate dielectric layer, an assist gate, an insulation layer, and a sacrificial layer stacked in order;
forming an isolation material layer on a sidewall of the at least one stacked structure;
forming a tunneling dielectric layer on the substrate at one side of the at least one stacked structure;
forming at least one floating gate on a sidewall of the isolation material layer and on the tunneling dielectric layer, wherein the at least one floating gate comprises:
an inner sidewall facing the sidewall of the isolation material layer;
a lateral sidewall; and
a curved sidewall connected to edges of the inner sidewall and the lateral sidewall;
etching the at least one stacked structure until an uppermost edge of the at least one floating gate is higher than a top surface of the insulation layer;
forming a dielectric material layer covering the inner sidewall, the lateral sidewall, and the curved sidewall of the at least one floating gate after etching the at least one stacked structure;
etching the dielectric material layer to form an etched dielectric material layer and expose the uppermost edge of the at least one floating gate; and
forming at least one upper gate structure on the etched dielectric material layer after etching the dielectric material layer, wherein a portion of the etched dielectric material layer is disposed between the at least one upper gate structure and the substrate, and the portion of the etched dielectric material layer is laterally separated from the assist gate.
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