US 12,279,421 B2
Semiconductor device
Sangyoun Jo, Suwon-si (KR); Kohji Kanamori, Seongnam-si (KR); Kwangyoung Jung, Hwaseong-si (KR); and Jeehoon Han, Hwaseong-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Mar. 27, 2023, as Appl. No. 18/190,253.
Application 18/190,253 is a continuation of application No. 17/155,225, filed on Jan. 22, 2021, granted, now 11,616,070, issued on Mar. 28, 2023.
Claims priority of application No. 10-2020-0069026 (KR), filed on Jun. 8, 2020.
Prior Publication US 2023/0262972 A1, Aug. 17, 2023
Int. Cl. H10B 41/27 (2023.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H10B 41/10 (2023.01); H10B 41/40 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/40 (2023.01)
CPC H10B 41/27 (2023.02) [H01L 23/5226 (2013.01); H01L 23/528 (2013.01); H10B 41/10 (2023.02); H10B 41/40 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/40 (2023.02)] 18 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first substrate including a first portion and a second portion spaced apart from the first portion, the first portion being a first polysilicon plate portion and the second portion being a second polysilicon plate portion;
a lower separation region including an insulating material between the first portion and the second portion;
a first stack structure on the first portion;
a second stack structure on the second portion and spaced apart from the first stack structure;
an intermediate stack structure between the first stack structure and the second stack structure, and spaced apart from the first and second stack structures;
first block separation structures penetrating through the first stack structure;
second block separation structures penetrating through the second stack structure; and
a contact plug penetrating through the intermediate stack structure,
wherein each of the first and second stack structures includes interlayer insulating layers and gate electrodes alternately stacked in a vertical direction,
wherein the intermediate stack structure includes first layers and second layers alternately stacked in the vertical direction,
wherein each of the first and second block separation structures extends in a first direction parallel to an upper surface of the first substrate,
wherein the contact plug does not vertically overlap with the first and second portions and is spaced apart from the first and second portions,
wherein lower surfaces of the first and second block separation structures are at a higher level than lower surfaces of the first and second portions where the first and second block separation structures contact the first and second portions, respectively,
wherein a material of the first layers is the same material as a material of the interlayer insulating layers, and
wherein an uppermost gate electrode of the gate electrodes is at a same level as an uppermost second layer of the second layers.