US 12,279,417 B2
Semiconductor structure and manufacturing method thereof
Xiang Liu, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Apr. 7, 2022, as Appl. No. 17/658,427.
Application 17/658,427 is a continuation of application No. PCT/CN2022/070757, filed on Jan. 7, 2022.
Claims priority of application No. 202110904551.0 (CN), filed on Aug. 6, 2021.
Prior Publication US 2023/0043347 A1, Feb. 9, 2023
Int. Cl. H10B 12/00 (2023.01); H01L 29/08 (2006.01)
CPC H10B 12/488 (2023.02) [H01L 29/0843 (2013.01); H10B 12/30 (2023.02)] 16 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a substrate, having a plurality of word line trenches and source/drain regions each adjacent to each word line trench; and
a plurality of word lines, each located in each word line trench and each comprising a first conductive layer, a single junction layer and a second conductive layer stacked in sequence, wherein, the first conductive layer is located at a bottom of the word line trench; a projection of the word line on a sidewall of the word line trench and a projection of a source/drain region on the sidewall of the word line trench have an overlapping region with a preset height; and in the case that a voltage applied to the word line is less than a preset voltage, a resistance of the single junction layer is greater than the preset resistance, to make the first conductive layer and the second conductive layer disconnected.