| CPC H10B 12/34 (2023.02) [H10B 12/0335 (2023.02); H10B 12/053 (2023.02); H10B 12/315 (2023.02)] | 20 Claims |
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1. A method of fabricating a semiconductor memory device, the method comprising:
patterning a substrate to form a first trench defining an active pattern;
forming a device isolation layer in the first trench;
forming a gate electrode to cross the active pattern and to extend in a first direction;
forming a first source/drain region and a second source/drain region in an upper portion of the active pattern, the first and second source/drain regions being adjacent to respective opposite sides of the gate electrode;
forming an insulating layer on the active pattern;
forming a line structure on the insulating layer to cross the active pattern and to extend in a second direction, the line structure comprising a bit line electrically connected to the first source/drain region and a mask pattern on the bit line;
forming a spacer on a side surface of the line structure;
forming a contact to penetrate the insulating layer and to be coupled to the second source/drain region;
forming a landing pad on the contact; and
forming a data storing element on the landing pad,
wherein the forming of the contact comprises:
performing an anisotropic etching process using the mask pattern and the spacer as a mask to form a first contact hole penetrating the insulating layer;
selectively recessing an upper portion of the device isolation layer exposed by the first contact hole to form a vertical extension hole exposing an upper side surface of the active pattern; and
forming a conductive material in the first contact hole and the vertical extension hole,
wherein during the anisotropic etching process, a top surface of the active pattern is recessed to form a recessed top surface.
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