| CPC H10B 12/30 (2023.02) [H01L 23/5223 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 28/60 (2013.01); H10B 12/03 (2023.02); H10B 12/05 (2023.02); H10B 20/20 (2023.02)] | 20 Claims |
|
1. A manufacturing method of an integrated circuit having a first region and a second region adjacent to the first region, comprising:
providing a substrate;
forming a first transistor over the substrate; and
forming an interconnect structure over the substrate, comprising:
forming dielectric layers; and
forming a memory module in the dielectric layers, comprising:
forming a first memory device in the first region, comprising:
forming a second transistor having a gate electrode;
forming a second memory device in the second region, comprising:
forming a bottom electrode, wherein the gate electrode of the second transistor of the first memory device and the bottom electrode of the second memory device are simultaneously formed; and
forming a third memory device above the first memory device and in the first region.
|