| CPC H10B 12/20 (2023.02) [G11C 11/404 (2013.01); G11C 11/4096 (2013.01)] | 8 Claims |
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1. A semiconductor memory device comprising:
a semiconductor base material that stands on a substrate in a vertical direction relative to the substrate or that extends along the substrate in a horizontal direction;
a first impurity layer and a second impurity layer that are disposed at respective ends of the semiconductor base material;
a first gate insulating layer that partially or entirely surrounds a side surface of the semiconductor base material between the first impurity layer and the second impurity layer and that is in contact with or in close vicinity to the first impurity layer;
a second gate insulating layer that partially or entirely surrounds the side surface of the semiconductor base material, that is connected to the first gate insulating layer, and that is in contact with or in close vicinity to the second impurity layer;
a first gate conductor layer that covers the first gate insulating layer;
a second gate conductor layer that covers the second gate insulating layer; and
a channel semiconductor layer that is the semiconductor base material and that is constituted by a first channel semiconductor layer covered by the first gate insulating layer and a second channel semiconductor layer covered by the second gate insulating layer, wherein
a memory write operation is performed by controlling voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity layer, and the second impurity layer to perform an operation of discharging a group of electrons among the group of electrons and a group of positive holes through the first impurity layer or the second impurity layer, the group of electrons and the group of positive holes being generated inside the channel semiconductor layer in a first boundary region between the first impurity layer and the channel semiconductor layer or in a second boundary region between the second impurity layer and the channel semiconductor layer by a gate-induced drain leakage current, and an operation of keeping some or all of the group of positive holes retained in the channel semiconductor layer, and
a memory erase operation is performed by controlling the voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity layer, and the second impurity layer to discharge the group of positive holes through either the first impurity layer or the second impurity layer or both the first impurity layer and the second impurity layer.
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