| CPC H10B 12/20 (2023.02) [G11C 11/404 (2013.01); G11C 11/4096 (2013.01)] | 18 Claims |
|
1. A memory device using a semiconductor device comprising:
a substrate;
a first semiconductor layer that is disposed on the substrate;
a first impurity layer that is disposed on a portion of a surface of the first semiconductor layer and at least a portion of which has a columnar shape;
a second impurity layer that is in contact with the portion of the first impurity layer having a columnar shape and that extends in a vertical direction;
a first insulating layer that covers a portion of the first semiconductor layer and a portion of the first impurity layer;
a first gate insulating layer that is in contact with the first insulating layer and that surrounds the first impurity layer and the second impurity layer;
a first gate conductor layer and a second gate conductor layer that are in contact with the first insulating layer and the first gate insulating layer;
a second insulating layer that is formed in such a manner as to be in contact with the first gate conductor layer, the second gate conductor layer, the first insulating layer, and the first gate insulating layer;
a second semiconductor layer that is in contact with the second impurity layer;
a second gate insulating layer that partially or entirely surrounds an upper portion of the second semiconductor layer;
a third gate conductor layer that partially or entirely covers an upper portion of the second gate insulating layer;
a third impurity layer and a fourth impurity layer each of which is in contact with one of two side surfaces of the second semiconductor layer located outside an end of the third gate conductor layer in a horizontal direction in which the second semiconductor layer extends;
a first wiring conductor layer that is connected to the third impurity layer;
a second wiring conductor layer that is connected to the fourth impurity layer;
a third wiring conductor layer that is connected to the third gate conductor layer;
a fourth wiring conductor layer that is connected to the first gate conductor layer; and
a fifth wiring conductor layer that is connected to the second gate conductor layer,
wherein a memory write operation is performed by performing an operation of generating a group of electrons and a group of holes in the second semiconductor layer and the second impurity layer by using impact ionization that is caused by a current supplied between the third impurity layer and the fourth impurity layer or by using a gate-induced drain leakage current, an operation of discharging minority carriers in the second semiconductor layer and the second impurity layer, the minority carriers being the generated group of electrons or the generated group of holes, and an operation of causing a subset or all of majority carriers in the second semiconductor layer and the second impurity layer, the majority carriers being the group of electrons or the group of holes, to remain in the second semiconductor layer and the second impurity layer by controlling voltages that are applied to the first wiring conductor layer, the second wiring conductor layer, the third wiring conductor layer, the fourth wiring conductor layer, and the fifth wiring conductor layer, and
wherein a memory erase operation is performed by extracting the majority carriers remaining in the second semiconductor layer, the majority carriers being the group of electrons or the group of holes, from at least one location of the first impurity layer, the third impurity layer, and the fourth impurity layer by controlling voltages that are applied to the first wiring conductor layer, the second wiring conductor layer, the third wiring conductor layer, the fourth wiring conductor layer, and the fifth wiring conductor layer.
|