| CPC H10B 12/05 (2023.02) [G11C 5/063 (2013.01); H10B 12/0335 (2023.02); H10B 12/31 (2023.02); H10B 12/482 (2023.02); H10B 12/488 (2023.02)] | 14 Claims |
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1. A memory device, comprising:
an array of vertically stacked memory cells, the array having horizontally oriented access devices and digit lines and vertically oriented access lines, comprising:
a layer of semiconductor material, a layer of a first dielectric material formed on the layer of semiconductor material, and a layer of a second dielectric material formed on the layer of first dielectric material, wherein the layers of the semiconductor material, the first dielectric material, and the second dielectric material are formed in repeating iterations to form a vertical stack;
the horizontally oriented access devices having a first source/drain region and a second source drain region separated by both an epitaxially grown single crystalline channel of a plurality of epitaxially grown single crystalline channels and a body region, and having gates opposing the channel and separated therefrom by a gate dielectric;
the vertically oriented access lines separated from the channel by the gate dielectric;
horizontally oriented storage nodes electrically coupled to the second source/drain regions of the horizontally oriented access devices, wherein each respective horizontally oriented storage node is formed on a same horizontal plane and level with a respective epitaxially grown single crystalline channel of the plurality of epitaxially grown single crystalline channels; and
the horizontally oriented digit lines electrically coupled to the first source/drain regions of the horizontally oriented access devices.
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