US 12,279,395 B2
Patterned bolster plate and composite back plate for semiconductor chip LGA package and cooling assembly retention
Phil Geng, Washougal, WA (US); Ralph V. Miele, Hillsboro, OR (US); David Shia, Portland, OR (US); Jeffory L. Smalley, Olympia, WA (US); Eric W. Buddrius, Hillsboro, OR (US); Sean T. Sivapalan, Portland, OR (US); Olaotan Elenitoba-Johnson, Tigard, OR (US); and Mengqi Liu, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 14, 2021, as Appl. No. 17/474,974.
Prior Publication US 2021/0410317 A1, Dec. 30, 2021
Int. Cl. H05K 7/14 (2006.01); H01L 23/053 (2006.01); H01L 23/32 (2006.01); H01L 23/40 (2006.01)
CPC H05K 7/1489 (2013.01) [H01L 23/053 (2013.01); H01L 23/32 (2013.01); H01L 23/40 (2013.01)] 14 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a bolster plate to be placed between a mass and an electronic circuit board, the mass to be placed in thermal contact with a semiconductor chip package, the semiconductor chip package to be placed within an outer frame of the bolster plate, the bolster plate having one or more inner support arms within the outer frame to form reduced openings in the bolster plate that are smaller than an area within the outer frame, at least a portion of the one or more inner support arms to reside between the semiconductor chip package and the electronic circuit board, the one or more inner support arms having one or more holes in which one or more studs from a back plate are to be inserted, the electronic circuit board to be placed between the bolster plate and the back plate.