	US 12,279,238 B2
	Interleaver design for multi-slot uplink shared channel transmission
Gokul Sridharan, Sunnyvale, CA (US); Seyedkianoush Hosseini, San Diego, CA (US); Hung Dinh Ly, San Diego, CA (US); and Peter Gaal, San Diego, CA (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Mar. 21, 2022, as Appl. No. 17/655,655.
Claims priority of provisional application 63/164,464, filed on Mar. 22, 2021.
Prior Publication US 2022/0303987 A1, Sep. 22, 2022
Int. Cl. H04W 72/0446 (2023.01)

CPC H04W 72/0446 (2013.01)

28 Claims

1. An apparatus for wireless communication, comprising:

a memory; and

one or more processors coupled to the memory, wherein the one or more processors are configured to:

select, for a communication on a multi-slot transmission occasion, coded bits of a plurality of coded bits on a per slot basis for each respective slot of multiple slots of the multi-slot transmission occasion;

interleave, based at least in part on the communication being associated with a modulation and coding scheme (MCS) that satisfies a threshold, the coded bits on a per slot basis to form one or more interleaved encoded bit sequences of a codeblock, wherein interleaving is deactivated for communications associated with an MCS that fails to satisfy the threshold; and

transmit the communication including the one or more interleaved encoded bit sequences.