US 12,279,062 B2
Image sensor and operation method thereof
Ping-Hung Yin, Taipei (TW); Jia-Shyang Wang, Miaoli (TW); and Jia-Sian Lyu, Pingtung (TW)
Assigned to Guangzhou Tyrafos Semiconductor Technologies Co., LTD, Guangzhou (CN)
Filed by Guangzhou Tyrafos Semiconductor Technologies Co., LTD, Guangzhou (CN)
Filed on Apr. 20, 2023, as Appl. No. 18/304,323.
Claims priority of provisional application 63/341,423, filed on May 13, 2022.
Prior Publication US 2023/0370751 A1, Nov. 16, 2023
Int. Cl. H04N 25/78 (2023.01); G06F 1/08 (2006.01); H01L 25/075 (2006.01); H01L 25/18 (2023.01); H03K 19/0185 (2006.01); H03L 7/099 (2006.01); H04N 25/60 (2023.01); H04N 25/627 (2023.01); H04N 25/63 (2023.01); H04N 25/709 (2023.01); H04N 25/76 (2023.01); H04N 25/77 (2023.01); H04N 25/772 (2023.01); H04N 25/778 (2023.01); H10F 39/00 (2025.01)
CPC H04N 25/78 (2023.01) [G06F 1/08 (2013.01); H01L 25/0753 (2013.01); H01L 25/18 (2013.01); H03K 19/018521 (2013.01); H03L 7/099 (2013.01); H04N 25/60 (2023.01); H04N 25/627 (2023.01); H04N 25/63 (2023.01); H04N 25/709 (2023.01); H04N 25/77 (2023.01); H04N 25/772 (2023.01); H04N 25/778 (2023.01); H04N 25/7795 (2023.01); H10F 39/026 (2025.01); H10F 39/8037 (2025.01); H10F 39/811 (2025.01)] 17 Claims
OG exemplary drawing
 
1. An image sensor, comprising:
a first pixel circuit, comprising:
a first pixel unit;
a first transfer transistor, wherein a first terminal of the first transfer transistor is coupled to a first floating diffusion node, and a second terminal of the first transfer transistor is coupled to the first pixel unit;
a first reset transistor, coupled to the first floating diffusion node;
a first readout transistor, wherein a control terminal of the first readout transistor is coupled to the first floating diffusion node; and
a first selection transistor, wherein a first terminal of the first selection transistor is coupled to the first readout transistor; and
a column readout circuit, comprising a first circuit node and a second circuit node,
wherein a first terminal of the first reset transistor and a first terminal of the first readout transistor are coupled to the first circuit node, and a second terminal of the first selection transistor is coupled to the second circuit node,
wherein the column readout circuit further comprises:
a first transistor, wherein a first terminal of the first transistor is coupled to a first operating voltage, and a second terminal of the first transistor is coupled to the first circuit node; and
a second transistor, wherein a first terminal of the second transistor is coupled to the first circuit node, and a second terminal of the second transistor is coupled to a first output terminal.