US 12,279,061 B2
MIPI C-PHY and D-PHY interface with shared driver, equalization, and data path circuitry
Jhankar Malakar, Corvallis, OR (US); and Arindam Raychaudhuri, Bangalore (IN)
Assigned to SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Scottsdale, AZ (US)
Filed by SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Scottsdale, AZ (US)
Filed on Mar. 13, 2023, as Appl. No. 18/182,644.
Prior Publication US 2024/0314466 A1, Sep. 19, 2024
Int. Cl. H04N 25/766 (2023.01); H04L 7/00 (2006.01); H04N 25/76 (2023.01); H04N 25/767 (2023.01)
CPC H04N 25/766 (2023.01) [H04N 25/767 (2023.01); H04N 25/7795 (2023.01); H04L 7/0087 (2013.01)] 20 Claims
OG exemplary drawing
 
1. Circuitry comprising:
a plurality of half-driver sub-circuits operable in
(1) a first mode in which the half-driver sub-circuits are coupled together in groups of two and
(2) a second mode in which the half-driver sub-circuits are coupled together in groups of three, wherein each half-driver sub-circuit in the plurality of half-driver sub-circuit comprises:
a pull-up path having one or more pull-up transistors, and
a pull-down path having one or more pull-down transistors.