US 12,278,886 B2
Hybrid serial receiver circuit
Ryan D. Bartling, Sunnyvale, CA (US); Jafar Savoj, Sunnyvale, CA (US); and Brian S. Leibowitz, San Francisco, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on May 8, 2023, as Appl. No. 18/313,729.
Application 18/313,729 is a continuation of application No. 17/482,302, filed on Sep. 22, 2021, granted, now 11,689,351.
Prior Publication US 2023/0283449 A1, Sep. 7, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H04L 7/00 (2006.01); H04L 25/03 (2006.01)
CPC H04L 7/0079 (2013.01) [H04L 7/0016 (2013.01); H04L 25/03878 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a front-end circuit configured to generate an equalized signal using at least one signal that encodes a serial data stream that includes a plurality of data symbols;
an ADC-based receiver circuit that includes a plurality of analog-to-digital converter circuits, wherein the ADC-based receiver circuit is configured, based on a baud rate of the serial data stream, to generate a first plurality of recovered data symbols using the equalized signal and a plurality of first clock signals;
a first analog receiver circuit configured, based on the baud rate of the serial data stream, to generate a second plurality of recovered data symbols using the equalized signal and a plurality of second clock signals; and
a multiplex circuit configured to select, based on the baud rate of the serial data stream, either the first plurality of recovered data symbols or the second plurality of recovered data symbols to generate a plurality of output data symbols.