| CPC H04L 7/0079 (2013.01) [H04L 7/0075 (2013.01)] | 35 Claims |
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1. A sparse data signal receiver system comprising: a mixer configured to generate a serial stream of mixed signals from a serial stream of sparse data signals and a serial stream of synchronization signals, to thereby add redundancy to said serial stream of sparse data signals and enable clock regeneration therefrom; a clock regeneration unit configured to operate on said serial stream of mixed signals; a data speed convertor configured to convert said serial stream of mixed signals into a stream of parallel mixed signals; and a demixer configured to remove the redundancy introduced by said mixer into said sparse data signals,
characterized in that
said serial stream of synchronization signals comprising a pseudo random binary sequence (PRBS), and said clock regeneration unit configured to determine a frequency of said serial stream of synchronization signals comprising said PRBS,
said system further comprising a synchronization signal emulation unit configured to: generate a PRBS signal having the frequency determined by said clock regeneration unit and periodicity of said PRBS; and produce a corresponding stream of parallel synchronization signals emulating said serial stream of synchronization signals comprising the PRBS and synchronized therewith, and
said demixer configured to generate a parallel stream of demixed signals from said stream of parallel synchronization signals having the determined frequency and the PRBS periodicity and said stream of parallel mixed signals.
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