US 12,278,863 B2
Gateway for connection to a host processor and multiple slaves and method for operating the gateway
Thomas Leitner, Dortmund (DE); Jens Voigt, Dortmund (DE); and Michael Küttner, Dortmund (DE)
Assigned to Elmos Semiconductor SE, Dortmund (DE)
Filed by Elmos Semiconductor SE, Dortmund (DE)
Filed on Oct. 12, 2023, as Appl. No. 18/485,892.
Claims priority of application No. 10 2022 210 908.2 (DE), filed on Oct. 14, 2022; and application No. 10 2022 210 909.0 (DE), filed on Oct. 14, 2022.
Prior Publication US 2024/0129364 A1, Apr. 18, 2024
Int. Cl. G06F 15/16 (2006.01); H04L 12/46 (2006.01); H04L 67/104 (2022.01); H04W 72/25 (2023.01); H04W 88/16 (2009.01); H04W 84/00 (2009.01); H04W 84/20 (2009.01)
CPC H04L 67/1044 (2013.01) [H04L 12/46 (2013.01); H04W 72/25 (2023.01); H04W 88/16 (2013.01); H04W 84/005 (2013.01); H04W 84/20 (2013.01)] 6 Claims
OG exemplary drawing
 
6. A method for operating a gateway for connection to a host processor and multiple slaves, the gateway and the slaves being organized in a point-to-point (P2P) topology such that the gateway has an independent channel for each of the slaves, the gateway being configured to:
receive multiple control signals, each control signal including at least one control signal for a particular predetermined slave from the multiple slaves, from the host processor;
determine whether the slaves for which the at least one control signal has been received are in an operational state; and
simultaneously output the control signals received from the host processor to the slaves for which the at least one control signal has been received only when all of the slaves for which the at least one control signal has been received are in the operational state, wherein the gateway includes:
a first interface for communication with the host processor by means of a first communication standard;
a second interface for communication with the slaves by means of a second communication standard; and
a memory connected to the first and/or to the second interface for the purpose of temporarily storing data that are received at the gateway via the first and/or the second interface,
wherein the memory is protected by means of an error detection method and/or an error correction method, the method comprising:
receiving multiple control signals, each comprising at least one control signal for a particular predetermined slave from the multiple slaves, at the gateway from the host processor;
determining whether the slaves for which the at least one control signal has been received are in an operational state;
simultaneously outputting the control signals received from the host processor to the slaves for which the at least one control signal has been received only when all of the slaves for which the at least one control signal has been received are in the operational state; and
protecting data received by means of the first and/or the second interface by means of an error detection method and/or an error correction method at the first interface, the second interface and/or the memory.