US 12,278,722 B2
Circuits and methods for wake-up receivers
Vivek Mangal, Santa Clara, CA (US); and Peter R. Kinget, Summit, NJ (US)
Assigned to The Trustees of Columbia University in the City of New York, New York, NY (US)
Filed by The Trustees of Columbia University in the City of New York, New York, NY (US)
Filed on Oct. 25, 2023, as Appl. No. 18/383,797.
Application 18/383,797 is a continuation of application No. 17/419,138, abandoned, previously published as PCT/US2020/012439, filed on Jan. 6, 2020.
Claims priority of provisional application 62/788,657, filed on Jan. 4, 2019.
Prior Publication US 2024/0073069 A1, Feb. 29, 2024
Int. Cl. H04L 27/06 (2006.01); H03K 19/0185 (2006.01); H03K 19/17788 (2020.01); H04L 27/26 (2006.01)
CPC H04L 27/06 (2013.01) [H03K 19/0185 (2013.01); H03K 19/17788 (2013.01); H04L 27/2617 (2013.01); H04L 27/26412 (2021.01)] 21 Claims
OG exemplary drawing
 
1. A receiver comprising:
a self-mixer including a plurality of inputs and an output;
a matched filter having an input and an output, wherein the input of the matched filter is coupled to the output of the self-mixer;
and
a charge pump having an input coupled to the output of the matched filter and having an output coupled to a first input of the plurality of inputs of the self-mixer,
wherein the self-mixer comprises:
a first Negative-Channel Metal-Oxide-Semiconductor (NMOS) transistor having a source, a drain, and a gate, wherein the drain of the first NMOS transistor is coupled to the output of the self mixer;
a second NMOS transistor having a source, a drain, and a gate, wherein the drain of the second NMOS transistor is connected to the source of the first NMOS transistor;
a third NMOS transistor having a source, a drain, and a gate, wherein the drain of the third NMOS transistor is connected to the source of the second NMOS transistor and wherein the gate of the third NMOS transistor is connected to the gate of the first NMOS transistor;
a fourth NMOS transistor having a source, a drain, and a gate, wherein the drain of the fourth NMOS transistor is connected to the source of the third NMOS transistor and wherein the gate of the fourth NMOS transistor is connected to the gate of the second NMOS transistor;
a first capacitor having a first side and a second side, wherein the first side of the first capacitor is connected to a second input of the plurality of inputs of the self-mixer and wherein the second side of the first capacitor is connected to the source of the first NMOS transistor;
a second capacitor having a first side and a second side, wherein the first side of the second capacitor is connected to the first side of the first capacitor and wherein the second side of the second capacitor is connected to the gate of the first NMOS transistor;
a third capacitor having a first side and a second side, wherein the first side of the third capacitor is connected to the first side of the first capacitor and wherein the second side of the third capacitor is connected to the source of the third NMOS transistor; and
a resistor have a first side and a second side, wherein the first side of the resistor is connected to a bias voltage and to the gate of the fourth NMOS transistor and wherein the second side of the resistor is connected to the gate of the third NMOS transistor.