| CPC H04L 25/03038 (2013.01) [H04L 7/0016 (2013.01)] | 20 Claims |
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1. An apparatus, comprising:
a delay circuit configured to receive a first signal that encodes a serial data stream that includes a plurality of data symbols, wherein the delay circuit includes a T-coil circuit and is configured to generate, based on the first signal, a first delayed signal at a center-tap junction of the T-coil circuit and a second delayed signal at an output junction of the T-coil circuit;
a front-end circuit, wherein the front-end circuit is an analog circuit comprising a continuous time linear equalizer (CTLE) and is configured to:
receive the first signal, the first delayed signal, and the second delayed signal, wherein the first signal is received without a delay being applied; and
generate an equalized signal using the first signal, the first delayed signal, and the second delayed signal, and wherein, to generate the equalized signal, the front-end circuit is configured to generate one or more cancellation signals to cancel a precursor present in the first signal and further configured to cancel a postcursor present in the first signal;
a sample circuit configured to sample the equalized signal to generate a plurality of samples; and
a recovery circuit configured to generate a plurality of recovered data symbols using the plurality of samples.
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