US 12,278,701 B2
High speed interconnect symbol stream forward error-correction
Nausheen Ansari, Folsom, CA (US); Ziv Kabiry, Haifa (IL); and Gal Yedidia, Haifa (IL)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by INTEL CORPORATION, Santa Clara, CA (US)
Filed on Mar. 22, 2024, as Appl. No. 18/613,935.
Application 18/613,935 is a continuation of application No. 17/967,125, filed on Oct. 17, 2022, granted, now 11,990,996.
Application 17/967,125 is a continuation of application No. 17/353,000, filed on Jun. 21, 2021, granted, now 11,522,640, issued on Dec. 6, 2022.
Application 17/353,000 is a continuation of application No. 16/524,613, filed on Jul. 29, 2019, granted, now 11,044,045, issued on Jun. 22, 2021.
Application 16/524,613 is a continuation of application No. 15/089,251, filed on Apr. 1, 2016, granted, now 10,367,605, issued on Jul. 30, 2019.
Claims priority of provisional application 62/188,109, filed on Jul. 2, 2015.
Prior Publication US 2024/0235733 A1, Jul. 11, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H04L 1/00 (2006.01); H03M 5/00 (2006.01); H03M 5/14 (2006.01); H03M 13/00 (2006.01); H03M 13/15 (2006.01); H03M 13/29 (2006.01); H03M 13/31 (2006.01)
CPC H04L 1/0057 (2013.01) [H03M 5/145 (2013.01); H03M 13/1515 (2013.01); H03M 13/2906 (2013.01); H03M 13/31 (2013.01); H04L 1/0041 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a transmitter; and
physical (PHY) layer circuitry for the transmitter, the PHY layer circuitry to:
encode symbols for a symbol stream;
interleave the symbols from the symbol stream to form interleaved forward error correction (FEC) blocks;
generate Reed Solomon (RS) parity symbols for the interleaved FEC blocks; and
generate a FEC symbol stream from the interleaved FEC blocks and the RS parity symbols.