US 12,278,672 B2
Computing apparatus and margin measurement method
Ryota Higashi, Tokyo (JP); and Masao Ogihara, Tokyo (JP)
Assigned to Hitachi, Ltd., Tokyo (JP)
Filed by Hitachi, Ltd., Tokyo (JP)
Filed on Sep. 8, 2022, as Appl. No. 17/940,569.
Claims priority of application No. 2021-203988 (JP), filed on Dec. 16, 2021.
Prior Publication US 2023/0198573 A1, Jun. 22, 2023
Int. Cl. H04B 3/487 (2015.01); H04L 25/08 (2006.01)
CPC H04B 3/487 (2015.01) [H04L 25/085 (2013.01)] 5 Claims
OG exemplary drawing
 
1. A computing apparatus, comprising:
a first apparatus and a second apparatus;
a differential transmission line that couples the first apparatus and the second apparatus to each other;
a current voltage source that applies noise to the differential transmission line; and
a processor coupled to a memory storing instructions to permit the processor to function as:
a noise control unit that controls the current voltage source; and
a margin measurement unit that measures an occurrence frequency of communication error between the first apparatus and the second apparatus; and
a crosstalk testing wiring that is disposed in parallel with a pair of signal lines included in the differential transmission line, over a predetermined section thereof,
wherein a distance from the crosstalk testing wiring to a first signal line making up the pair of signal lines is different from a distance from the crosstalk testing wiring to a second signal line making up the pair of signal lines, and
wherein the current voltage source applies voltage to the crosstalk testing wiring.