US 12,278,657 B2
Method and apparatus to optimize power clamping
Rong Jiang, San Diego, CA (US); Khushali Shah, San Diego, CA (US); and Peter Bacon, Derry, NH (US)
Assigned to pSemi Corporation, San Diego, CA (US)
Filed by pSemi Corporation, San Diego, CA (US)
Filed on Feb. 23, 2024, as Appl. No. 18/585,690.
Application 18/585,690 is a continuation of application No. 18/159,296, filed on Jan. 25, 2023, granted, now 11,923,883.
Application 18/159,296 is a continuation of application No. 17/384,518, filed on Jul. 23, 2021, granted, now 11,569,857, issued on Jan. 31, 2023.
Application 17/384,518 is a continuation of application No. 16/808,315, filed on Mar. 3, 2020, granted, now 11,075,661, issued on Jul. 27, 2021.
Prior Publication US 2024/0275416 A1, Aug. 15, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H04B 1/18 (2006.01); G05F 1/59 (2006.01); H03F 3/189 (2006.01); H03G 1/00 (2006.01); H03G 3/30 (2006.01); H03H 7/24 (2006.01); H03H 7/38 (2006.01); H03K 5/08 (2006.01)
CPC H04B 1/18 (2013.01) [G05F 1/59 (2013.01); H03F 3/189 (2013.01); H03G 1/0088 (2013.01); H03G 3/3042 (2013.01); H03H 7/24 (2013.01); H03H 7/38 (2013.01); H03K 5/08 (2013.01); H03F 2200/294 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An RF front end including:
(a) an input selection switch having at least one input and a plurality of outputs, the input selection switch configured to selectively couple a selected one of the at least one input to a selected one of the plurality of outputs;
(b) a direct gain path coupled to a first of the plurality of outputs;
(c) a bypass path coupled to a second of the plurality of outputs;
(d) an output selection switch having a first input coupled to the direct gain path, a second input coupled to the bypass path, and an output, the output selection switch configured to selectively couple the direct gain path or the bypass path to the output of the output selection switch; and
(e) a clamping circuit coupled in series with the bypass path between the input selection switch and the output selection switch, the clamping circuit including:
(1) an input terminal coupled to the bypass path;
(2) an output terminal coupled to the bypass path;
(3) a reference potential terminal;
(4) a bypass switch coupled between the input terminal and the output terminal;
(5) a signal path coupled in series between the input terminal and the output terminal and in parallel with the bypass switch, the signal path including a first signal path switch and a second signal path switch coupled in series; and
(6) a clamping device coupled between a node between the first and the second signal path switches and the reference potential terminal.