US 12,278,653 B2
Delta sigma modulator
Naoki Terao, Tokyo (JP); Munehiko Nagatani, Tokyo (JP); and Hideyuki Nosaka, Tokyo (JP)
Assigned to Nippon Telegraph and Telephone Corporation, Tokyo (JP)
Appl. No. 18/041,968
Filed by Nippon Telegraph and Telephone Corporation, Tokyo (JP)
PCT Filed Sep. 15, 2020, PCT No. PCT/JP2020/034883
§ 371(c)(1), (2) Date Feb. 16, 2023,
PCT Pub. No. WO2022/059060, PCT Pub. Date Mar. 24, 2022.
Prior Publication US 2024/0030933 A1, Jan. 25, 2024
Int. Cl. H03M 3/00 (2006.01)
CPC H03M 3/39 (2013.01) [H03M 3/344 (2013.01); H03M 3/43 (2013.01); H03M 3/454 (2013.01); H03M 3/458 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A delta sigma modulator for modulating an input signal to output an output signal, the delta sigma modulator comprising:
an integrator configured to integrate differences between the input signal and the output signal; and
a clocked comparator configured to output a result of comparison between an output of the integrator and a threshold at timing synchronized with a clock signal, the result being output as the output signal, wherein the integrator includes:
an operational amplifier including an input terminal and an output terminal;
an input resistor that has a first end to which the input signal is input, and a second end connected to the input terminal of the operational amplifier;
a feedback capacitor that is connected between the input terminal and the output terminal of the operational amplifier;
an inductor that is connected in parallel to the input resistor; and
an integrated circuit package;
wherein the operational amplifier, the input resistor, and the feedback capacitor are disposed in the integrated circuit package, wherein the feedback capacitor is disposed between the input terminal and the output terminal of the operational amplifier; and
wherein the inductor is disposed outside the integrated circuit package.