| CPC H03M 3/352 (2013.01) [H03M 3/376 (2013.01)] | 5 Claims |
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1. A device comprising:
an input adder with a positive input coupled to an input signal and a negative input coupled to a feedback signal;
a first integrator with a data input coupled to an output of the input adder and a reset input coupled to an output of a reset circuit;
a plurality of downstream integrators, each downstream integrator comprising a data input and a reset input, wherein the data inputs of the plurality of downstream integrators are connected in series, wherein the input of the first of the plurality of downstream integrators is coupled to an output of the first integrator, and wherein the plurality of downstream integrators comprises a last integrator and wherein the reset input of the plurality of downstream integrators are respectively coupled to an output of the reset circuit;
an output adder with inputs coupled, respectively, to the output of the first integrator, to the output of one or more of the plurality of downstream integrators, and to an output of a feedforward path, the feedforward path comprising a gain stage coupled between the input signal and the output adder;
a quantizer with an input coupled to the output of the output adder, the quantizer to generate a quantized output signal;
a digital-to-analog converter with an input coupled to the quantized output signal and an output comprising the feedback signal;
wherein the reset circuit to generate a first reset signal to be coupled to the reset input of the first integrator and one or more second reset signals to be coupled to the reset inputs of, respectively, the plurality of downstream integrators, the first reset signal and the second reset signal to be de-asserted at different times, and
the first reset signal to be asserted during a first sample of the quantized output signal and to be de-asserted after the first sample of the quantized output signal.
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