US 12,278,643 B2
Calibration for DTC fractional frequency synthesis
Somnath Kundu, Hillsboro, OR (US); Stefano Pellerano, Beaverton, OR (US); and Brent R. Carlton, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 22, 2021, as Appl. No. 17/481,827.
Prior Publication US 2023/0098856 A1, Mar. 30, 2023
Int. Cl. H03L 7/197 (2006.01); H03L 7/091 (2006.01); H03L 7/099 (2006.01)
CPC H03L 7/1976 (2013.01) [H03L 7/091 (2013.01); H03L 7/0995 (2013.01)] 25 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a digital-to-time converter (DTC) to generate a DTC clock signal based on a received input clock frequency and a received initial digital input code;
a phase-lock loop (PLL) to generate a PLL clock signal based on a received PLL input;
a binary phase-detector (PD) to generate a PD output based on a comparison between the DTC clock signal and the PLL clock signal;
a plurality of calibration bins, each of the plurality of calibration bins associated with one of a plurality of DTC calibration range portions, each of the plurality of calibration bins to generate a signed accumulated PD portion based on the PD output, the signed accumulated PD portion associated with one of the plurality of DTC calibration range portions; and
an adder to generate a calibrated DTC input code based on a combination of the signed accumulated PD portion and a subsequent digital input code;
wherein the DTC is further to generate a calibrated clock signal based on the calibrated DTC input code.