US 12,278,642 B2
Clock synchronization
Ya-Wei Huang, Milpitas, CA (US)
Assigned to NXP USA, Inc., Austin, TX (US)
Filed by NXP USA, Inc., Austin, TX (US)
Filed on Nov. 22, 2022, as Appl. No. 17/992,852.
Prior Publication US 2024/0171185 A1, May 23, 2024
Int. Cl. H03L 7/195 (2006.01); H03L 7/23 (2006.01); H03L 7/24 (2006.01)
CPC H03L 7/195 (2013.01) [H03L 7/23 (2013.01); H03L 7/24 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A time-synchronization apparatus, comprising:
inputs for receiving a reference pulse train and a local clock signal;
a frequency offset acquisition and compensation (FOAC) module configured to identify a frequency offset by implementing a frequency-offset-acquisition process which includes counting cycles of the local clock signal within a period of the reference pulse train; and
a joint phase and residual frequency offset tracking (JPRFOT) module configured to determine a phase offset of the local clock signal, output the phase offset, generate a residual frequency error based on the phase offset, and provide the residual frequency error to the FOAC module,
wherein the FOAC module is further configured to generate at least one timer-adjustment signal based on the frequency offset and the residual frequency error and output said at least one timer-adjustment signal;
wherein the phase offset of the local clock signal is determined in reference to a second reference pulse train; and
wherein the second reference pulse train has a frequency of at least 10 times the frequency of the reference pulse train.