US 12,278,641 B2
Phase-lock loop circuit, voltage-controlled oscillator and compensation method
Cheng-Feng Shih, Hsinchu (TW); and Jui-Hsien Fang, Hsinchu (TW)
Assigned to NUVOTON TECHNOLOGY CORPORATION, Hsinchu (TW)
Filed by NUVOTON TECHNOLOGY CORPORATION, Hsinchu (TW)
Filed on Mar. 24, 2023, as Appl. No. 18/189,769.
Claims priority of application No. 111124886 (TW), filed on Jul. 4, 2022.
Prior Publication US 2024/0007114 A1, Jan. 4, 2024
Int. Cl. H03K 3/03 (2006.01); H03K 5/01 (2006.01); H03L 7/099 (2006.01); H03K 5/00 (2006.01)
CPC H03L 7/099 (2013.01) [H03K 3/0322 (2013.01); H03K 5/01 (2013.01); H03L 7/0995 (2013.01); H03K 2005/00078 (2013.01)] 3 Claims
OG exemplary drawing
 
1. A voltage-controlled oscillator for a phase-lock loop circuit, utilized to receive a control voltage and generate a clock signal, wherein the voltage-controlled oscillator comprises:
a voltage-to-current device, configured to generate a linear current based on the control voltage;
a process compensation device, configured to generate a compensation current based on the control voltage, wherein the compensation current is proportional to a transistor operation speed corresponding to a process offset;
a subtraction unit, electrically connected to the voltage-to-current device and the process compensation device, and configured to subtract the compensation current from the linear current to generate a control current; and
a clock signal generating module, electrically connected to the subtraction unit, and configured to generate the clock signal based on the control current,
wherein the process compensation device comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor and a resistor, and
wherein a source of the first PMOS transistor and a source of the second PMOS transistor are electrically connected to a supply voltage, a gate of the first PMOS transistor and a gate of the second PMOS transistor are electrically connected to each other, a drain of the first PMOS transistor is electrically connected to a drain of the first NMOS transistor, a drain of the second PMOS transistor is electrically connected to a drain of the second NMOS transistor, a gate of the first NMOS transistor is configured to receive the control voltage, a source of the first NMOS transistor is electrically connected one end of the resistor, the other end of the resistor is electrically connected to a low voltage, a gate of the second NMOS transistor is electrically connected to the subtraction unit and the drain of the second NMOS transistor, and a source of the second NMOS transistor is electrically connected to the low voltage.