US 12,278,639 B1
Wide frequency range burst mode clock and data recovery circuit using clock to data delay compensation method
Mikhail Tamrazyan, Hsin-Chu (TW); and Vinod Kumar Jain, Hsin-Chu (TW)
Assigned to Faraday Technology Corp., Hsin-Chu (TW)
Filed by Faraday Technology Corp., Hsin-Chu (TW)
Filed on Oct. 16, 2023, as Appl. No. 18/380,635.
Int. Cl. H03D 3/24 (2006.01); H03L 7/08 (2006.01); H03L 7/091 (2006.01); H03L 7/093 (2006.01)
CPC H03L 7/0807 (2013.01) [H03L 7/091 (2013.01); H03L 7/093 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A clock and data recovery (CDR) circuit, comprising:
a frequency tracking loop for generating an output signal frequency locked with a reference clock, comprising:
an injection locked oscillator, for receiving a voltage control signal generated according to the reference clock, and adjusting a frequency of oscillation to generate an output signal having a frequency tracked to the reference clock frequency, and then receiving an input data signal and extracting an output clock from the input data signal; and
a phase tracking circuit coupled to the frequency tracking loop, comprising:
a phase interpolator, coupled to the injection locked oscillator, for receiving the output clock and adjusting a phase of the output clock according to an input code to generate a sampling clock for sampling a signal to generate a deserialized signal; and
a finite state machine, coupled to the phase interpolator, for outputting a code to the phase interpolator according to the deserialized signal of a multiplexer in order to adjust the phase of the output clock.