US 12,278,638 B2
Droop detection and control of digital frequency-locked loop
Kaushik Mazumdar, Waltham, MA (US); Ashish Jain, Austin, TX (US); Joyce Cheuk Wai Wong, Toronto (CA); and Mikhail Rodionov, Richmond Hill (CA)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US); and ATI Technologies ULC, Markham (CA)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US); and ATI Technologies ULC, Markham (CA)
Filed on Nov. 30, 2023, as Appl. No. 18/525,071.
Application 18/525,071 is a continuation in part of application No. 17/557,590, filed on Dec. 21, 2021, granted, now 11,942,953.
Prior Publication US 2024/0106438 A1, Mar. 28, 2024
Int. Cl. H03L 7/08 (2006.01); G01R 19/165 (2006.01)
CPC H03L 7/08 (2013.01) [G01R 19/16552 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
a power supply monitor operable to provide a trigger signal in response to a power supply voltage dropping below a threshold voltage;
a clock generator operable to provide a first clock signal having a frequency dependent on a value of a frequency control word, and to change the frequency of the first clock signal over time using a native slope in response to a change in the frequency control word; and
a divider responsive to an assertion of the trigger signal to divide a frequency of the first clock signal by a divide value to provide a second clock signal.