US 12,278,637 B2
HDLC data reception using signal pulse widths
Roshan K. Barua, Medford, MA (US); Gregg Norris, Rockport, MA (US); and Feng Wang, Salem, MA (US)
Assigned to Applied Materials, Inc., Santa Clara, CA (US)
Filed by Applied Materials, Inc., Santa Clara, CA (US)
Filed on Dec. 19, 2022, as Appl. No. 18/084,202.
Prior Publication US 2024/0204762 A1, Jun. 20, 2024
Int. Cl. H03K 7/08 (2006.01); H04J 3/24 (2006.01)
CPC H03K 7/08 (2013.01) [H04J 3/247 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A microcontroller for receiving HDLC (High-level Data Link Control) packets, comprising:
a processing unit;
an edge detector/timer circuit;
a memory device in communication with the processing unit, containing instructions, which when executed by the processing unit, enable the microcontroller to:
use the edge detector/timer circuit to record durations of a plurality of pulse widths of an incoming signal, wherein the incoming signal is a HDLC packet;
determine a bit rate based on the durations of the plurality of pulse widths; and
reconstruct the HDLC packet based on the bit rate previously determined,
wherein an array of pulse widths is stored, and the processing unit uses values in the array of pulse widths to determine a bit time, defined as a time to transmit one bit, and divides the array of pulse widths by the bit time to create an array of bit pulse widths, where each value in the array of bit pulse widths is indicative of a number of bits in each pulse.