US 12,278,636 B2
Receiver circuit with automatic DC offset cancellation in display port applications
Hongquan Wang, Shanghai (CN); Shengyuan Zhang, Shanghai (CN); Qing Chen, Nanjing (CN); Liang Xu, Shanghai (CN); and Kochung Lee, San Jose, CA (US)
Assigned to PARADE TECHNOLOGIES, LTD., San Jose, CA (US)
Filed by PARADE TECHNOLOGIES, LTD., San Jose, CA (US)
Filed on Nov. 28, 2022, as Appl. No. 18/070,283.
Prior Publication US 2024/0178826 A1, May 30, 2024
Int. Cl. H03K 5/24 (2006.01); G09G 5/00 (2006.01); H03H 7/06 (2006.01)
CPC H03K 5/24 (2013.01) [G09G 5/006 (2013.01); H03H 7/06 (2013.01); G09G 2370/00 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An electronic device, comprising:
an input interface configured to receive a differential input signal carrying digital serial data;
a reference interface configured to provide a predefined reference voltage;
a high pass filter coupled to the input interface, the high pass filter configured to filter the differential input signal and generate a filtered differential input signal;
a differential integrator coupled to the high pass filter and the reference interface, the differential integrator configured to receive the filtered differential input signal and generate a differential output signal including a first output signal and a second output signal, each of the first and second output signals having a common mode output voltage substantially equal to the predefined reference voltage;
a comparator including an operational amplifier, the comparator coupled to the differential output signal of the differential integrator, wherein the operational amplifier has no feedback and is configured to convert the first output signal and the second output signal, which share the common mode output voltage, to an output digital signal that recovers the digital serial data carried by the differential input signal; and
a connector including a plurality of data lanes and a pair of differential command pins, the pair of differential command pins distinct from the plurality of data lanes and coupled to the input interface, wherein:
the input interface receives the differential input signal via the pair of differential command pins; and
the differential input signal includes a serial data command configured to control data transmission via the plurality of data lanes of the connector.