US 12,278,635 B2
Configuration of aggressor integrated circuit to prevent spur interference at victim integrated circuit
Helena Deidre O'Shea, San Jose, CA (US); Ali Moaz, Bayern (DE); Tim Schoenauer, Bavaria (DE); and Rahmi Hezar, San Francisco, CA (US)
Assigned to APPLE INC., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Aug. 25, 2023, as Appl. No. 18/456,364.
Application 18/456,364 is a continuation of application No. 17/977,191, filed on Oct. 31, 2022, granted, now 11,777,479.
Application 17/977,191 is a continuation of application No. 17/469,294, filed on Sep. 8, 2021, granted, now 11,522,531.
Prior Publication US 2024/0056066 A1, Feb. 15, 2024
Int. Cl. H03K 5/1252 (2006.01); G06F 21/71 (2013.01)
CPC H03K 5/1252 (2013.01) [G06F 21/71 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
determining a relationship between a first local clock signal of a first integrated circuit (IC) and a second local clock signal of a second IC based on a reference signal;
generating at least one spur parameter indicative of a frequency drift between the first local clock signal and the second local clock signal based on the relationship and operation information indicative of a repeating sequence of operating intervals of the second IC; and
mitigating at least one spur based on the at least one spur parameter.