a self-shielding circuit, configured to: receive an initial command signal and N initial clock signals, register the initial command signal according to a first initial clock signal among the N initial clock signals that triggers the initial command signal at earliest, shield other N−1 second initial clock signals among the N initial clock signals, and output N intermediate command signals, where N is an integer greater than or equal to 2, and the N initial clock signals have a same frequency and different phases; and

a delay, electrically connected to the self-shielding circuit, and configured to: receive the N intermediate command signals and the N initial clock signals, and delay and output the N intermediate command signals to obtain a delayed command signal;

wherein the self-shielding circuit comprises:

a shielding circuit, configured to receive the N initial clock signals and output N intermediate clock signals; wherein the N intermediate clock signals comprise a first intermediate clock signal that is valid and N−1 second intermediate clock signals that are invalid; and

a register, electrically connected to the shielding circuit, and configured to: receive the initial command signal and the N intermediate clock signals, register the initial command signal according to the first intermediate clock signal, and obtain and output the N intermediate command signals.