US 12,278,624 B2
Logic circuit for providing a signal value after a predetermined time period and method of using same
Nastaran Nayebpanah, Brossard (CA); and Jeffrey Weinstein, Cote St. Luc (CA)
Assigned to PRATT & WHITNEY CANADA CORP., Longueuil (CA)
Filed by Pratt & Whitney Canada Corp., Longueuil (CA)
Filed on Feb. 11, 2022, as Appl. No. 17/670,128.
Prior Publication US 2023/0261649 A1, Aug. 17, 2023
Int. Cl. H03K 17/56 (2006.01); G06F 9/44 (2018.01); G06F 30/327 (2020.01); H03K 5/01 (2006.01); G06F 9/4401 (2018.01); G06F 9/445 (2018.01); H03K 5/00 (2006.01)
CPC H03K 17/56 (2013.01) [G06F 30/327 (2020.01); H03K 5/01 (2013.01); G06F 9/4411 (2013.01); G06F 9/44505 (2013.01); H03K 2005/00078 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A logic circuit comprising:
a timer having a time constant TM; and
a plurality of switch assemblies comprising M number of switch assemblies, the plurality of switch assemblies in signal communication with the timer, the plurality of switch assemblies including a signal input and a signal output, the plurality of switch assemblies configured to provide a signal value of the signal input to the signal output after a predetermined N value of time delay, each switch assembly of the plurality of switch assemblies including:
a switch including a true input gate, a false input gate, and an output gate;
a first delay in signal communication with the output gate; and
a second delay in signal communication between the output gate and the false input gate;
wherein the timer constant TM is substantially equal to the predetermined N value of time delay divided by the M number of switch assemblies such that the plurality of switch assemblies is configured to update the signal output at an interval corresponding to the timer constant TM.