US 12,278,622 B2
RF switch with compensation and gate bootstrapping
Semen Syroiezhin, Erlangen (DE); Valentyn Solomko, Munich (DE); and Ivan Jevtic, Nuremberg (DE)
Assigned to Infineon Technologies AG, Neubiberg (DE)
Filed by Infineon Technologies AG, Neubiberg (DE)
Filed on Jan. 8, 2024, as Appl. No. 18/406,982.
Application 18/406,982 is a division of application No. 17/185,564, filed on Feb. 25, 2021, granted, now 11,916,546.
Prior Publication US 2024/0154610 A1, May 9, 2024
Int. Cl. H03K 17/16 (2006.01); H03K 17/041 (2006.01); H03K 17/14 (2006.01); H03K 17/74 (2006.01); H04B 1/44 (2006.01)
CPC H03K 17/16 (2013.01) [H03K 17/04106 (2013.01); H03K 17/74 (2013.01); H03K 17/145 (2013.01); H03K 2217/0054 (2013.01); H03K 2217/0081 (2013.01); H04B 1/44 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A radio frequency (RF) switch device comprising:
a first transistor and a second transistor, wherein the first and second transistors are coupled in series at a first source/drain terminal of the second transistor to establish a switchable RF path;
a first compensation network coupled between a body terminal of the first transistor and a second source/drain terminal of the second transistor, wherein the first compensation network is configured to establish a path for current flowing between the body terminal of the first transistor and the second source/drain terminal of the second transistor in a first direction and to block current flowing therebetween in a second direction opposite to the first direction;
a first bootstrapping network having a first terminal coupled to a first bias terminal, a second terminal coupled to a gate terminal of the first transistor, and a third terminal coupled to an internal node of the first compensation network, wherein the first bootstrapping network is configured to establish a low impedance path between the gate terminal and the body terminal of the first transistor in response to a first voltage value of the first bias terminal, and wherein the first bootstrapping network is configured to establish a high impedance path between the gate terminal and the body terminal of the first transistor in response to a second voltage value of the first bias terminal; and
a first resistor divider including a first resistor and a second resistor and having a first terminal, a second terminal, and a tap defined at an interconnection of the first resistor and second resistor, the second terminal directly coupled to a first source/drain terminal of the first transistor, and the first terminal directly coupled to a second source/drain terminal of the first transistor, wherein the first terminal of the first bootstrapping network is directly coupled to the tap of the first resistor divider.