US 12,278,601 B2
Power amplifier semiconductor device
Akihiko Nishio, Ishikawa (JP); Katsuhiko Kawashima, Hyogo (JP); Yusuke Kanda, Toyama (JP); and Takashi Yui, Shiga (JP)
Assigned to NUVOTON TECHNOLOGY CORPORATION JAPAN, Kyoto (JP)
Filed by Nuvoton Technology Corporation Japan, Kyoto (JP)
Filed on Sep. 25, 2024, as Appl. No. 18/895,976.
Application 18/895,976 is a continuation of application No. PCT/JP2023/006448, filed on Feb. 22, 2023.
Claims priority of provisional application 63/324,957, filed on Mar. 29, 2022.
Prior Publication US 2025/0015768 A1, Jan. 9, 2025
Int. Cl. H03F 3/195 (2006.01); H01L 23/66 (2006.01); H03F 3/21 (2006.01); H10D 30/01 (2025.01); H10D 30/47 (2025.01); H10D 64/00 (2025.01); H10D 64/27 (2025.01)
CPC H03F 3/21 (2013.01) [H01L 23/66 (2013.01); H03F 3/195 (2013.01); H10D 30/015 (2025.01); H10D 30/475 (2025.01); H10D 64/111 (2025.01); H10D 64/411 (2025.01); H01L 2223/6616 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A power amplifier semiconductor device in which a plurality of unit high electron mobility transistors (HEMTs) are connected in parallel, the power amplifier semiconductor device comprising:
a substrate;
a semiconductor layer provided on a surface of the substrate and including the plurality of unit HEMTs;
a connection layer provided on the semiconductor layer and including a source electrode, a drain electrode, and a gate electrode of each of the plurality of unit HEMTs;
a terminal layer provided on the connection layer and including a source pad, a drain pad, and a gate pad respectively connected to the source electrode, the drain electrode, and the gate electrode of each of the plurality of unit HEMTs via a first portion of a wiring layer;
a back electrode which is provided on a bottom surface of the substrate and whose potential is set to a source potential equal to a potential of the source electrode; and
substrate vias that pass through the substrate and have a shield wiring layer on inner walls of the substrate vias, the shield wiring layer being a second portion of the wiring layer whose potential is set to the source potential, wherein
each of the drain electrode and the gate electrode comprises drain electrodes and gate electrodes, respectively, corresponding to the plurality of unit HEMTs,
the power amplifier semiconductor device further comprises:
a drain aggregation portion in which the drain electrodes are collectively connected by wires in a third portion of the wiring layer; and
a gate aggregation portion in which the gate electrodes are collectively connected by wires in a fourth portion of the wiring layer, and
in a plan view of the substrate, either one of the drain aggregation portion or the gate aggregation portion is or both of the drain aggregation portion and the gate aggregation portion are each surrounded by the substrate vias.