US 12,278,600 B2
Amplifier bias circuit
John P. Bettencourt, Boxford, MA (US); Valery S. Kaper, Winchester, MA (US); and Steven M. Lardizabal, Westford, MA (US)
Assigned to Raytheon Company, Arlington, VA (US)
Filed by Raytheon Company, Waltham, MA (US)
Filed on Dec. 28, 2021, as Appl. No. 17/646,162.
Prior Publication US 2023/0208364 A1, Jun. 29, 2023
Int. Cl. H03F 1/22 (2006.01); H03F 3/04 (2006.01); H03F 3/193 (2006.01); H03F 1/30 (2006.01)
CPC H03F 3/193 (2013.01) [H03F 1/223 (2013.01); H03F 1/301 (2013.01); H03F 1/302 (2013.01); H03F 2200/451 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A circuit, comprising:
an amplifier including first and second transistors coupled in a stacked configuration;
a first current mirror having a first control loop and a first mirror transistor coupled to a terminal of the first transistor to provide a first bias current, wherein the first current mirror includes the first mirror transistor, a first fixed current source, and a first follower transistor coupled to the first mirror transistor in a follower configuration;
a second current mirror having a second control loop and a second mirror transistor coupled to a terminal of the second transistor to provide a second bias current; and
a reference transistor coupled to the first and second current mirrors.