US 12,278,598 B2
Parallelized low noise amplifiers for a quantum computer
Mridula Prathapan, Zurich (CH); Thomas Morf, Gross (CH); Peter Mueller, Zurich (CH); Marcel A. Kossel, Reichenburg (CH); Bogdan Cezar Zota, Rueschlikon (CH); and Pier Andrea Francese, Adliswil (CH)
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Feb. 21, 2022, as Appl. No. 17/651,829.
Prior Publication US 2023/0268890 A1, Aug. 24, 2023
Int. Cl. H03F 1/26 (2006.01); G06N 10/20 (2022.01); H03F 1/02 (2006.01); H03F 1/56 (2006.01)
CPC H03F 1/26 (2013.01) [G06N 10/20 (2022.01); H03F 1/0211 (2013.01); H03F 1/56 (2013.01); H03F 2200/294 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A low noise amplifier circuit comprising:
a plurality of input stages, each input stage being coupled to one or more qubits, wherein the plurality of input stages comprises one or more input matching networks, and a transistor, wherein each input matching network comprises a plurality of passive components, the plurality of passive components including one or more passive components selected from the group consisting of: one or more resistors, one or more inductors, and one or more capacitors;
a shared output stage coupled to the plurality of input stages; and
a voltage controller coupled to the plurality of input stages and the shared output stage, wherein the voltage controller is configured to selectively activate an input stage of the plurality of input stages in order to read a qubit coupled to the input stage.