| CPC H03F 1/223 (2013.01) [H03F 3/193 (2013.01); H03F 3/45071 (2013.01); H03F 2200/21 (2013.01)] | 21 Claims | 

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               1. A circuital arrangement comprising: 
            a stacked transistor amplifier coupled between a supply voltage and a reference ground, the stacked transistor amplifier comprising a N-type transistor stack in series connection with a P-type transistor stack; 
                a first resistive ladder coupled between the supply voltage and a first current source, respective nodes of the first resistive ladder coupled to gates of a respective input transistor and respective one or more cascode transistors of the P-type transistor stack; 
                a second resistive ladder coupled between a second current source and the reference ground, respective nodes of the second resistive ladder coupled to gates of a respective input transistor and respective one or more cascode transistors of the N-type transistor stack; 
                a P-type current mirror coupled to the first resistive ladder; and 
                an N-type current mirror coupled to the second resistive ladder, 
                wherein voltages at the respective nodes of the first resistive ladder are based on a difference between a fixed current output by the first current source and an adjustable current output by the P-type current mirror, and 
                wherein voltages at the respective nodes of the second resistive ladder are based on a difference between a fixed current output by the second current source and an adjustable current output by the N-type current mirror. 
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