US 12,278,567 B2
Communication apparatus and semiconductor device
Takaaki Shimizu, Tokyo (JP); and Jun Ihara, Kitamoto Saitama (JP)
Assigned to Kabushiki Kaisha Toshiba, Tokyo (JP); and Toshiba Electronic Devices & Storage Corporation, Tokyo (JP)
Filed by KABUSHIKI KAISHA TOSHIBA, Tokyo (JP); and TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION, Tokyo (JP)
Filed on Sep. 9, 2022, as Appl. No. 17/941,681.
Claims priority of application No. 2022-034687 (JP), filed on Mar. 7, 2022.
Prior Publication US 2023/0283187 A1, Sep. 7, 2023
Int. Cl. H02M 3/335 (2006.01); H02M 1/08 (2006.01); H04B 5/00 (2024.01); H04B 5/22 (2024.01)
CPC H02M 3/33523 (2013.01) [H02M 1/08 (2013.01); H04B 5/22 (2024.01)] 18 Claims
OG exemplary drawing
 
1. A communication apparatus comprising a transmitting circuit, wherein
the transmitting circuit includes an encoder, and
the encoder includes
a main pulse signal generation circuit configured to generate a first main pulse signal in response to rising of a logic signal, and a second main pulse signal in response to falling thereof,
a sub pulse signal generation circuit configured to perform at least either a first generation process of generating a first sub pulse signal corresponding to the first main pulse signal at predetermined intervals after a predetermined time from generation of the first main pulse signal, or a second generation process of generating a second sub pulse signal corresponding to the second main pulse signal at predetermined intervals after a predetermined time from generation of the second main pulse signal, and
an output circuit configured to output at least any of the first main pulse signal, the second main pulse signal, the first sub pulse signal, and the second sub pulse signal, and
the output circuit stops outputting at least either the first sub pulse signal or the second sub pulse signal.