US 12,278,559 B2
Power factor correction circuit
Michael Papini, Indianapoolis, IN (US)
Assigned to DRP Holdings LLC, Indianapolis, IN (US)
Filed by DRP Holdings LLC, Indianapolis, IN (US)
Filed on Jan. 2, 2024, as Appl. No. 18/402,066.
Application 18/402,066 is a continuation of application No. 17/720,800, filed on Apr. 14, 2022, granted, now 11,870,339.
Prior Publication US 2025/0015712 A1, Jan. 9, 2025
This patent is subject to a terminal disclaimer.
Int. Cl. H02M 1/42 (2007.01); G05F 1/70 (2006.01); H02M 3/155 (2006.01); H02P 23/26 (2016.01)
CPC H02M 1/4216 (2013.01) [H02M 3/155 (2013.01); G05F 1/70 (2013.01); H02M 1/4208 (2013.01); H02M 1/4225 (2013.01); H02M 1/4266 (2013.01); H02P 23/26 (2016.02)] 20 Claims
OG exemplary drawing
 
1. A power factor correction circuit, comprising:
a first RC circuit including a first resistor and a first capacitor electrically connected to a first node and a second node, wherein the first and second nodes are electrically connected to separate terminals of an AC power source;
a second separate RC circuit including a second resistor and second capacitor electrically connected to the first node and the second node;
wherein the first resister is electrically connected in parallel with the first capacitor, and wherein the second resistor is electrically connected in parallel with the second capacitor.