US 12,278,512 B2
Multi load and multi battery system with sharing apparatuses
Jeffrey Schline, Portland, OR (US); Samantha Rao, Bengaluru (IN); Naoki Matsumura, San Jose, CA (US); Ramon Cancel Olmo, Hillsboro, OR (US); Tod Schiff, Portland, OR (US); and Arunthathi Chandrabose, Bangalore (IN)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 23, 2020, as Appl. No. 17/132,771.
Prior Publication US 2021/0135478 A1, May 6, 2021
Int. Cl. H02J 7/00 (2006.01); G06F 1/3212 (2019.01); G06F 1/3287 (2019.01)
CPC H02J 7/007182 (2020.01) [G06F 1/3212 (2013.01); G06F 1/3287 (2013.01); H02J 7/0014 (2013.01); H02J 7/0063 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a first battery coupled to a first load via a first power supply rail, the first load including a processor;
a second battery coupled to a second load via a second power supply rail;
a plurality of switches coupled to the first load and the second load;
logic to determine whether a state of charge of the first battery is approximately equal to a state of charge of the second battery, and in response to such determination the logic is to turn on the plurality of switches to couple the second battery to the first load if a demand by the processor is bursty; and
a first charger; and a first battery transistor controllable by the first charger, wherein the first battery transistor is coupled to the first power supply rail, wherein the logic is to turn on the first battery transistor when the demand is bursty; and
a second charger and a second battery transistor controllable by the second charger, wherein the second battery transistor is coupled to the second power supply rail, wherein the logic is to turn on the second battery transistor when the demand is bursty.