US 12,278,508 B2
Single inductor multiple output charger for multiple battery applications
Yen-Mo Chen, Morrisville, NC (US); Sungkeun Lim, Cary, NC (US); and Qian Sun, Milpitas, CA (US)
Assigned to Renesas Electronics America Inc., Milpitas, CA (US)
Filed by Renesas Electronics America Inc., Milpitas, CA (US)
Filed on Jun. 15, 2020, as Appl. No. 16/901,673.
Claims priority of provisional application 62/862,422, filed on Jun. 17, 2019.
Prior Publication US 2020/0395774 A1, Dec. 17, 2020
Int. Cl. H02J 7/00 (2006.01); H02J 3/38 (2006.01)
CPC H02J 7/00047 (2020.01) [H02J 7/0013 (2013.01); H02J 7/0045 (2013.01); H02J 7/007182 (2020.01); H02J 3/38 (2013.01); H02J 2207/20 (2020.01)] 19 Claims
OG exemplary drawing
 
1. A device comprising:
a first subsystem configured to couple with a second subsystem, the first subsystem configured to operate in a plurality of alternating charging modes and including a first pair of back-to-back input transistors, wherein each of the input transistors of the first pair of back-to-back input transistors comprise electrically connected drain terminals and electrically connected gate terminals to provide a first input voltage to the first subsystem;
a first inductor electrically coupled with a first inductor node;
a first transistor directly electrically connected with the first inductor node at the source of the first transistor and a first output node at a drain of the first transistor and providing a first output voltage based on the first input voltage provided by the first pair of back-to-back input transistors;
a first battery electrically coupled with the first output node, the first battery having a first voltage capacity;
a second transistor electrically connected with the first output node, via a first output resistor, at a drain terminal of the second transistor and directly electrically connected to the first battery at a source terminal of the second transistor;
the second subsystem configured to couple with the first subsystem at either the first output node or a second output node, the second subsystem configured to operate in a plurality of alternating charging modes in cooperation with the first subsystem and including a second pair of back-to-back input transistors, wherein each of the input transistors of the second pair of back-to-back input transistors comprise electrically connected drain terminals and electrically connected gate terminals to provide a second input voltage to the second subsystem;
a third transistor electrically connected with the first inductor node at a source terminal of the third transistor and the second output node at a drain terminal of the third transistor providing a second output voltage based on the first input voltage;
a fourth transistor electrically connected with the second output node at a drain terminal of the fourth transistor;
a second battery electrically coupled with the second output node, the second battery having a second voltage capacity; and
the first transistor, the second transistor, the third transistor, and the fourth transistor electrically coupled with and activated and deactivated by a controller,
wherein the first subsystem and the second subsystem are electrically coupled in parallel with both the first output node and second output node, and the first battery and the second battery.