| CPC H02J 50/80 (2016.02) [H02J 50/12 (2016.02)] | 21 Claims |

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1. A power transmitter comprising:
an output circuit comprising a transmitter coil, wherein the transmitter coil is arranged to generate a power transfer signal in response to a drive signal applied to the output circuit;
a driver circuit, wherein the driver circuit is arranged to generate the drive signal;
a first communicator circuit comprising:
a memory circuit,
wherein the memory circuit is arranged to store a plurality of reference chip sequences,
wherein each reference chip sequence is linked to a data symbol;
a correlator circuit, wherein each correlator circuit is arranged to correlate a first chip sequence received from the power receiver with the plurality of reference chip sequences; and
a demodulator circuit,
wherein the first communicator circuit is arranged to receive symbols,
wherein the symbols are transmitted from a power receiver by load modulation of the power transfer signal,
wherein each symbol is represented by a chip sequence,
wherein the chip sequence is a sequence of modulation load values,
wherein each symbol is synchronized with the power transfer signal;
wherein the demodulator circuit is arranged to determine a first received data symbol as a data symbol linked to a reference chip sequence with a highest correlation with the first chip sequence,
wherein the first communicator circuit is arranged to synchronize a sampling of a signal of the output circuit to the power transfer signal.
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